A double data rate (DDR) memory interface (JEDEC JESD79-3E) has conventionally been present as a high speed memory interface standard. The DDR memory interface is used for RAM that is used in a personal computer and configured by a semiconductor circuit, such as, for example, a DDR synchronous dynamic random access memory (SDRAM).
With the DDR memory interface, content can be written to and read from RAM according to a request (command) from a memory controller. The DDR memory is memory that transfers data at a data transfer rate that is twice as high as the clock frequency by inputting and outputting the data at both the rising edge (positive edge) and the falling edge (negative edge) of the clock signal.
The DDR memory transmits to a dual in-line memory module (DIMM), an internal clock signal (CK signal) generated in the memory controller. The DIMM generates a data strobe signal (DQS signal) using the CK signal received from the DDR memory and transmits the DQS signal together with data signals (DQ signals) to the memory controller.
The memory controller receives the DQS and the DQ signals, retimes the DQ signals using the DQS signal, and newly employs the internal clock. In this case, to securely receive the data signals using a latch circuit at the reception point, the timing relation between the internal CK signal and the received data signal needs to be within a specific range.
According to a related technique, when a signal is to be delayed for a time period from the input thereof to the output thereof, the necessary delay time period is generated by disposing a circuit to generate a fine delay and a circuit to generate a coarse delay, and using a combination of the circuits (see, e.g., Japanese Laid-Open Patent Publication No. 2009-130455).
However, when a reading operation is executed, the time period from the time when the memory controller issues a read command until the time when the DQS and the DQ signals return to the memory controller (=flight time) varies. Factors causing variations may include, for example, the positions of the memory controller and the DIMM, the power source, and environmental variations such as temperature variations. When multi-slot DIMMs are mounted on the same DIMM channel, the variation differs according to the DIMM slot to be accessed.
When reading operations or writing operations are successively executed for multiple slots, suppression of the variation while the slots are switched at a high speed is difficult.